Integrated circuits are commonly fabricated by first forming an ingot of a single crystal semiconductor material, typically silicon, which is sliced into thin wafers. A thin epitaxial layer of semiconductor material, typically silicon, having a controlled amount of impurities, is then grown on the wafer. Thereafter, at least one passivation layer (typically SiO.sub.2) is formed over the epitaxial layer. One or more windows (features) are created through the passivation layer by the process of photolithography. Creation of the windows by the process of photolithography is accomplished by first applying a coating of photoresist to the passivation layer. Thereafter, the coating of photoresist is selectively exposed to radiation through a photomask. The photoresist is developed, causing the nonexposed portions thereof to be washed away. The wafer is then etched, thereby creating windows within those areas on the surface of the passivation layer not covered by the photoresist.
Once the windows have been created in the passivation layer, then impurities may be introduced therethrough into the wafer. After introduction of the impurities, one or more additional layers are successively formed over the passivation layer. One or more windows may be created through each additional layer by the above-described process of photolithography prior to formation of the next layer thereover. Typically, such windows are created for the purpose of making electrical connections between layers. Depending on the type of integrated circuit to be fabricated, as many as nine different layers may be formed on the wafer, each layer having at least one window therethrough.
It is extremely important that the windows through each layer above the passivation layer be precisely located a predetermined lateral distance relative to each window through the latter. Even a very small registration error between the windows through the passivation layer and the windows in any of the wafer layers thereabove may render the integrated circuits produced from the wafer inoperative. Such registration errors are due primarily to a misalignment between the passivation layer and the photomask used to expose the resist pattern on the overlying wafer layer.
To detect for such misalignment, each of a first set of spaced vernier patterns is etched into the passivation layer simultaneously with the formation of the windows therethrough. Thereafter, a next layer is formed over the passivation layer. Resist is then applied to the overlying wafer layer. The resist is exposed and developed not only to create windows therein (to establish the design of the windows through the layer overlying the passivation layer) but also to create a vernier pattern overlapping one of the vernier patterns on the passivation layer. Typically, the passivation layer is light transmissive so the overlapping pair of vernier patterns can be seen by looking at the patterned resist on the overlying wafer layer.
Each of the first set of vernier patterns etched into the passivation layer, as well as the vernier pattern formed by patterning the resist on the overlying wafer layer, is comprised of a plurality of thin bars, usually 2-3 microns wide. The bars of each vernier pattern on the passivation layer are spaced a distance D apart whereas the bars of the vernier pattern formed by patterning the resist on the overlying wafer layer are spaced D+.delta. apart. Typical values for D and .delta. are 15 microns and 0.125 microns, respectively. The value of .delta. corresponds to the precision to which the offset error between a pair of overlapping vernier patterns can be resolved.
The point at which one of the vernier patterns on the passivation layer is said to be aligned with the overlapping vernier pattern on the wafer layer thereabove occurs where one of the bars of the former appears spaced between a pair of bars of the latter. The lateral offset between the pair of overlapping vernier patterns is given by the product of .delta. and n where n is the number of bars separating the best centered bar of the one vernier pattern on the passivation layer from a known reference point. Usually, the reference point is located at the center of the one vernier pattern. The lateral offset between the overlapping pair of vernier patterns is representative of the misalignment between the passivation layer and the photomask used to expose the resist on the wafer layer thereabove.
Presently, the lateral offset between the pair of overlapping vernier patterns is determined (read) manually. Usually, only one or two wafers in a given lot is actually inspected for this purpose. An operator typically places the wafer to be inspected on the stage of a microscope and identifies which of the bars of the vernier pattern on the passivation layer is best centered between a pair of bars of the vernier pattern on the overlying wafer layer. If the offset error between the pair of overlapping vernier patterns exceeds a desired production tolerance value, the resist on the layer overlying the passivation layer of each wafer in the lot is stripped therefrom. The misalignment between the passivation layer and the photomask previously employed to expose the resist on the overlying layer of each wafer is then corrected. Thereafter, resist is re-applied to each wafer and is again patterned so as to create the vernier pattern on the overlying layer thereof as well as the desired windows therethrough. The offset error between the pair of overlapping vernier patterns on one or two of the wafers in the lot is again read, and if the lateral offset is within production tolerances, the wafers are then etched.
After etching, another layer may be grown over the just-etched layer on each wafer. Resist is applied to this newly formed layer on each wafer and then is patterned to create a vernier pattern thereon as well as the desired windows therethrough to establish the location of the windows through this newly formed layer. The vernier pattern on this newly formed layer on each wafer is situated in registration with an opening through the layer therebeneath so as to overlap another of the first set of vernier patterns on the passivation layer. Again, at least one sample wafer is selected and the offset between the newly created vernier pattern and one of the vernier patterns on the passivation layer is then read. The wafers within the lot are either etched or their resist layer on each is stripped therefrom, depending on the magnitude of the offset error.
Before each newly formed layer on the wafer is etched to create windows therethrough, the offset between the vernier pattern thereon formed by the patterned resist and an underlying one of the vernier patterns on the passivation layer is read. Often, there may be as many as nine separate layers grown over the passivation layer, so there will be nine separate pairs of overlapping vernier patterns which must be read to determine the offset error therebetween. It is extremely desirable that the reading of the offset error between each pair of overlapping vernier patterns be as accurate as possible to avoid large overlay errors which can decrease manufacturing yields.
Unfortunately, manual reading of the offset between each pair of overlapping vernier patterns does not always afford a very high degree of accuracy. Many times the operator may experience difficulty in determining which of the bars of one of the pair of overlapping vernier patterns is best centered between a pair of bars of the other. Sometimes, several bars of one of the overlapping vernier patterns may appear to be best centered because of the small offset between the vernier patterns. Other factors which contribute to reading of the offset between a pair of overlapping vernier patterns are: (1) a lack of contrast between the vernier patterns formed on the wafer layers, (2) a shallow depth of focus of the microscope objective, and (3) operator eye strain.
The highest accuracy commonly achieved by manual reading of the offset between a pair of overlapping vernier patterns is on the order of .+-..delta./2. However, this level of accuracy may not be sufficient in the future as the size of, and the spacing between, the windows through the wafer layers shrinks.
Thus, there is a need for a technique for automatically determining the lateral offset between a pair of overlapping vernier patterns with a high degree of accuracy.